1. Technical Field
The present invention relates to a method for forming transistor of semiconductor device, and more particularly to a improved method for forming transistor of semiconductor device wherein a thermal oxide film is formed of an edge portion of a gate electrode by a thermal oxidation process on a gate electrode to reduce parasitic capacitance generated from overlapping between a drain region and a gate electrode region.
2. Description of the Related Art
The size of transistor has been reduced as the integration density and the operation speed of semiconductor devices is increased. As a result, the size of source/drain region is reduced and internal electrical resistance of the device is increased.
As the dimension of the transistor becomes smaller, the degree of overlapping between a gate electrode and a source/drain region increases, resulting in generation of a parasitic capacitance at the overlapping portion of an edge portion of the gate electrode and the source/drain region. This overlapping increase gate induced drain leakage (GIDL) which increases power consumption and reduces the operation speed of the device to degrade the characteristics of the device.
FIGS. 1a through 1c are cross-sectional diagrams illustrating sequential steps of a conventional method for manufacturing a transistor.
Referring to FIG. 1a, a device isolation film (not shown) defining an active region is formed on a semiconductor substrate 1, and an oxide film (not shown) and a conductive layer for gate electrode (not shown) are then sequentially formed in the active region.
Thereafter, the oxide film (not shown) and the conductive layer for gate electrode (not shown) are patterned by a selective etching process using a mask for gate electrode (not shown) to form a dummy gate 7 including a stacked structure of a gate oxide film 3 and a gate electrode 5.
Then, a low concentration P+impurity junction region 9 is formed on the active region of the semiconductor substrate 1 using the dummy gate 7 as an etching mask.
Referring to FIG. 1b, a halo-doped region 11 is formed on the substrate 1 below the impurity junction region 9.
Referring to FIG. 1c, an insulating film (not shown) is formed on entire surface of the resultant structure, and then etched to form an insulating film spacer 13.
FIG. 2 is a graph illustrating junction leakage current according to a bias voltage applied to a drain region of a conventional transistor. When the bias voltage Biasdrain[V] increases and a difference of gate voltage Vg varies from 2 to xe2x88x922 volt, the leakage current Lleak[K] increases.
In order to solve foregoing problem, a process of re-oxidizing the insulating film spacer 13 is introduced in the conventional method, but the process has been found to be ineffective.
Improved methods for forming a transistor of a semiconductor substrate are disclosed wherein parasitic capacitance is reduced by thermally oxidizing an edge portion of gate oxide film to increase the thickness of the gate oxide film between the gate electrode and an impurity junction region under the edge portion of the gate electrode.
One disclosed method comprises;
forming a dummy gate having a stacked structure of a gate oxide film and a gate electrode on a semiconductor substrate;
forming a first insulating film on the entire surface of the resultant structure;
over-etching the first insulating film to form first insulating film spacers on the lower portion of both sidewalls of the dummy gate;
forming a second insulating film on entire surface of the resultant structure;
etching the second insulating film to form second insulating film spacers on the upper portion of the both sidewalls of the dummy gate;
removing the first insulating film spacers to form openings each of which exposes the sidewall of the gate oxide film;
performing a thermal oxidation process to form a thermal oxide film filling up the opening;
ion-implanting low concentration impurities onto the substrate using the dummy gate and the second insulating film spacer as a mask to form a low concentration impurity junction regions on both sides of the dummy gate; and
performing a halo implant process using the dummy gate and the second insulating film spacer as a mask to form a halo doped region which is disposed under the both low concentration impurity junction regions and extends into the channel region under the dummy gate.
Here, it is preferable that an oxide film is formed on entire surface including the dummy gate electrode at a thickness ranging from 100 to 300 xc3x85, then over-etched to form the first insulating film spacer at lower sidewalls of the dummy gate electrode. The first insulating film spacer has a height of less than 300 xc3x85, preferably ranging from 50 to 100 xc3x85.
It is preferable that a material selected from the group consisting of nitride and alumina is formed on the entire surface of the resultant structure, and then etched to form the second insulating film spacer at upper sidewalls of the dummy gate electrode, the entire portion of the first insulating film spacer at a thickness ranging from 100 to 300 xc3x85.
The opening exposing a gate oxide film is preferably formed by removing the first insulating film spacer using a difference in etching selectivity between the semiconductor substrate and the second insulating film spacer.
The thermal oxidation process of the exposed gate oxide film is preferably performed at a temperature ranging from 850 to 1000xc2x0 C. The thermal oxide film preferably has a thickness ranging from 200 to 500 xc3x85.
It is preferable that the ion-implanting process of low concentration impurity and the halo implant process are tilt ion-implanting processes having a tilt angle ranging from 7xc2x0 to 15xc2x0 and from 30xc2x0 to 70xc2x0, respectively, with respect to the vertical direction to the surface of the semiconductor substrate.
The halo implant process, so called a pocket implant process, is introduced to inhibit a short channel effect generated from decrease of channel length of MOSFET, wherein the substrates is preferably implanted with a p-type and a n-type impurities in case of NMOS and PMOS, respectively, to partially increase a doping concentration of channel.
The halo implant process may also decrease depletion layers a bias is applied to effectively inhibiting short channel effects such as DIBL (drain induced barrier lowering).
According to the above-described method for forming a transistor, the parasitic capacitance at the edge portion of dummy gate electrode which occurs from overlapping of drain region and gate electrode region is reduced by thermally oxidizing the edge portion of the gate insulating film exposed through an opening to thicken the gate insulating film. As a result, the degradation of device characteristics due to GIDL may be prevented.